More DSE guidance

Working safely with display screen equipment

How to protect workers’ health.

The diagram in the Appendix provides a guide to setting up DSE workstations correctly. This can be given to DSE users and posted up in PC labs or at shared workstations. This can be given to DSE users and posted up in PC labs or at shared workstations. Working safely with display screen equipment. As an employer, you must protect your workers from the health risks of working with display screen equipment (DSE), such .

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An investment in the securities involves certain risks. Any representation to the contrary is a criminal offense. Terms continued from previous page: HSBC has filed a registration statement including a prospectus, a prospectus supplement and an Equity Index Underlying Supplement with the SEC for the offering to which this free writing prospectus relates.

You should read this document together with the related Equity Index Underlying Supplement, prospectus supplement and prospectus, each of which can be accessed via the hyperlinks below. The prospectus supplement dated March 5, at: The prospectus dated March 5, at: The securities are not deposit liabilities or other obligations of a bank and are not insured or guaranteed by the Federal Deposit Insurance Corporation or any other governmental agency of the United States or any other jurisdiction, and involve investment risks including possible loss of the stated principal amount invested due to the credit risk of HSBC.

Contingent Income Auto-Callable Securities. The contingent quarterly payment, if any, will be payable quarterly on the contingent payment date which is the 3rd business day after the related determination date or the maturity date, as applicable. It is possible that the closing level of one or more underlying indices could remain below their respective coupon barrier levels for extended periods of time or even throughout the term of the securities so that you may receive few or no contingent quarterly payments.

If the determination closing level of each underlying index is greater than or equal to its initial index level on any of the first 11 determination dates, the securities will be automatically redeemed for an early redemption payment equal to the stated principal amount plus the contingent quarterly payment with respect to the related determination date.

If the securities have not previously been redeemed and the final index level of each underlying index is greater than or equal to its downside threshold level, the payment at maturity will be the stated principal amount and, if the final index level of each underlying index is greater than or equal to its coupon barrier level, the contingent quarterly payment with respect to the final determination date. Investors in the securities must be willing to accept the risk of losing their entire principal and also the risk of not receiving any contingent quarterly payments.

In addition, investors will not participate in any appreciation of any of the underlying indices. The securities offer investors an opportunity to earn a contingent quarterly payment at an annual rate of at least 8. The securities may be redeemed prior to maturity for the stated principal amount per security plus the applicable contingent quarterly payment, and the payment at maturity will vary depending on the final index level of the worst performing underlying index, as follows:.

On any of the first 11 determination dates, the determination closing level of each underlying index is greater than or equal to its initial index level. The securities are not automatically redeemed prior to maturity and the final index level of each underlying index is greater than or equal to its downside threshold level. The securities are not automatically redeemed prior to maturity and the final index level of any underlying index is less than its downside threshold level. How the Securities Work.

The following diagrams illustrate the potential outcomes for the securities depending on 1 the determination closing level and 2 the final index level of each underlying index.

First 11 Determination Dates. In Examples 1 and 2, the closing levels of the underlying indices fluctuate over the term of the securities and the determination closing level of each underlying index is greater than or equal to its hypothetical initial index level on one of the first 11 determination dates.

Because the determination closing level of each underlying index is greater than or equal to its initial index level on one of the first 11 determination dates, the securities are automatically redeemed following the relevant determination date. In Examples 3 and 4, the determination closing level of at least one underlying index on the first 11 determination dates is less than its initial index level, and, consequently, the securities are not automatically redeemed prior to, and remain outstanding until, maturity.

In this example, the early redemption feature limits the term of your investment to approximately 3 months and you may not be able to reinvest at comparable terms or returns. If the securities are redeemed early, you will not receive any additional contingent quarterly payments. In this example, the early redemption feature limits the term of your investment to approximately 30 months and you may not be able to reinvest at comparable terms or returns. Examples 3 and 4 illustrate the payment at maturity per security based on the final index level of the worst performing underlying index.

In this example, the amount of cash that you would receive at maturity is significantly less than the stated principal amount. In addition, you would not be entitled to receive any contingent quarterly payments during the term of the securities. The securities may be suitable for you if: The securities may not be suitable for you if: Investing in the securities is not equivalent to investing directly in the securities comprising the underlying indices. You should understand the risks of investing in the securities and should reach an investment decision only after careful consideration, with your advisors, of the suitability of the securities in light of your particular financial circumstances and the information set forth in this free writing prospectus and the accompanying Equity Index Underlying Supplement, prospectus supplement and prospectus.

You will be subject to significant risks not associated with conventional fixed-rate or floating-rate debt securities. Pursuant to the terms of the securities, you agree to treat a security for U. Holders should note that the entire amount of the contingent quarterly payments will be subject to U. We do not plan to request a ruling from the IRS regarding the tax treatment of the securities, and the IRS or a court may not agree with the tax treatment described herein.

In , the U. While it is not clear whether the securities would be viewed as similar to the prepaid forward contracts described in the notice, it is possible that any U. Treasury Department regulations or other guidance issued after consideration of these issues could materially and adversely affect the tax consequences of an investment in the securities, possibly with retroactive effect. The notice focuses on a number of issues, the most relevant of which for holders of the securities are the character and timing of income or loss and the degree, if any, to which income realized by non-U.

Holders should consult their tax advisors regarding the U. Information about the Underlying Indices. The RTY is a capitalization-weighted index of stocks of component companies. It is designed to measure performance of the broad domestic economy through changes in the aggregate market value of stocks of component companies representing all major industries.

The top 5 industry groups by market capitalization as of July 31, were: The following graph sets forth the historical performance of the RTY based on its daily historical official closing level from January 2, through August 25, The official closing level for the RTY on August 25, was 1, The historical performance of the RTY should not be taken as an indication of its future performance, and no assurance can be given as to the level of the RTY at any time, including on the determination dates.

January 2, to August 25, The underlying index is a capitalization-weighted index of U. It is designed to measure performance of the broad domestic economy through changes in the aggregate market value of stocks representing all major industries. The following graph sets forth the historical performance of the SPX based on its daily historical official closing level from January 2, through August 25, The historical performance of the SPX should not be taken as an indication of its future performance, and no assurance can be given as to the level of the SPX at any time, including on the determination dates.

Additional Information About the Securities. Please read this information in conjunction with the summary terms on the front cover and page 2 of this document. In that case, the scheduled trading day preceding the date of acceleration will be used as the final determination date for purposes of determining the final index level of each underlying index.

If a market disruption event exists with respect to an underlying index on that scheduled trading day, then the accelerated final determination date for the applicable underlying index will be postponed for up to 5 scheduled trading days in the same manner used for postponing the originally scheduled final determination date.

The accelerated maturity date will then be the 3rd business day following the postponed accelerated final determination date. If the securities have become immediately due and payable following an event of default, you will not be entitled to any additional payments with respect to the securities.

This free writing prospectus relates to an offering of securities linked to the underlying indices. We reserve the right to withdraw, cancel or modify this offering and to reject orders in whole or in part.

Although the offering of the securities relates to the underlying indices, you should not construe that fact as a recommendation as to the merits of acquiring an investment linked to the underlying indices or as to the suitability of an investment in the securities. HSBC has filed a registration statement including a prospectus, a prospectus supplement and Equity Index Underlying Supplement with the SEC for the offering to which this free writing prospectus relates.

You should read this document together with the prospectus dated March 5, , the prospectus supplement dated March 5, and the Equity Index Underlying Supplement dated March 5, If the terms of the securities offered hereby are inconsistent with those described in the accompanying prospectus supplement, prospectus, or Equity Index Underlying Supplement, the terms described in this free writing prospectus shall control. We urge you to consult your investment, legal, tax, accounting and other advisors before you invest in the securities.

You may access these documents on the SEC web site at www. The Equity Index Underlying Supplement at: The prospectus supplement at: September 21, 3 business days after the pricing date. September 19, subject to adjustment as described in the accompanying Equity Index Underlying Supplement. The early redemption payment will be an amount equal to i the stated principal amount plus ii the contingent quarterly payment with respect to the related determination date.

With respect to each underlying index, its official closing level on any determination date other than the final determination date, as determined by the calculation agent. The securities will not be listed on any securities exchange. Commissions and issue price: With respect to each determination date other than the final determination date, the 3rd business day after the related determination date. The payment of the contingent quarterly payment, if any, with respect to the final determination date will be made on the maturity date.

With respect to each underlying index, its official closing level on the pricing date. With respect to each underlying index, its official closing level on the final determination date. Worst performing underlying index: The underlying index with the largest percentage decrease from its initial index level to its final index level.

The estimated initial value of the securities will be less than the price you pay to purchase the securities. The estimated initial value does not represent a minimum price at which we or any of our affiliates would be willing to purchase your securities in the secondary market, if any, at any time. The estimated initial value will be calculated on the pricing date and will be set forth in the pricing supplement to which this free writing prospectus relates.

Hypothetical Initial Index Level:. With respect to each underlying index, In Example 1 , the securities are automatically redeemed following the 1st determination date as the determination closing level of each underlying index on the 1st determination date is greater than or equal to its initial index level. You would receive the early redemption payment, calculated as follows:.

You would receive no contingent payment with respect to the 2nd through the 9th determination date, since the determination closing level of at least one underlying index on each of those determination dates is less than its. The securities are automatically redeemed following the 10th determination date, as the determination closing level of each underlying index on that day is greater than or equal to its initial index level.

In Example 3 , the closing level of at least one underlying index is below its coupon barrier level on every determination date. As a result, you would not receive any contingent quarterly payments during the term of the securities and, at maturity, you would be fully exposed to the decline in the closing level of the RTY, which is the worst performing underlying index.

As the final index level of the worst performing underlying index is less than its downside threshold level, your payment at maturity is calculated as follows:.

In Example 4 , the closing level of at least one underlying index is below its coupon barrier level on each of the 1st through the 11th determination date. As a result, the contingent quarterly payment is not payable for any of those determination dates. At maturity, because the final index level of each underlying index is greater than its downside threshold level, you would receive the stated principal amount.

However, because neither of the underlying indices is less than its coupon barrier level, you would also receive the contingent quarterly payment with respect to the final determination date. You may lose your entire initial investment. The securities do not guarantee any return of principal. The securities differ from ordinary debt securities in that we will not necessarily pay the full principal amount of the securities at maturity. HSBC will only pay you the principal amount of your securities at maturity if the securities have not been automatically redeemed prior to maturity and the final index level of each underlying index is greater than or equal to its downside threshold level.

If the final index level of any underlying index is less than its respective downside threshold level, you will be exposed to the decline in the closing level of the worst performing underlying index, as compared to its initial index level, on a 1 to 1 basis and you will receive for each security that you hold at maturity an amount equal to the stated principal amount times the index performance factor of the worst performing underlying index.

You will not receive any contingent quarterly payment for any quarterly period where the determination closing level or the final index level, as applicable, of any underlying index is less than its respective coupon barrier level on the related determination date. A contingent quarterly payment will be made with respect to a quarterly period only if the determination closing level or the final index level of each underlying index is greater than or equal to its coupon barrier level on the related determination date.

It is possible that the closing level of each underlying index could be below its respective coupon barrier level on most or all of the determination dates so that you will receive few or no contingent quarterly payments. Investors will not participate in any appreciation of any underlying index, and your return on the securities is limited to the principal amount plus any contingent quarterly payments, regardless of any appreciation in the levels of the underlying indices.

Investors will not participate in any appreciation of any underlying index from its initial index level. Unless the final index level of any underlying index is less than its coupon barrier level, you will receive at maturity the stated principal amount plus the contingent quarterly payment with respect to the final determination date, regardless of any appreciation in the levels of the underlying indices, which may be significant. The return on the securities will be limited to the contingent quarterly payment that is payable with respect to each determination date on which the determination closing level or the final index level, as applicable, of each underlying index is greater than or equal to its coupon barrier level.

Accordingly, the return on the securities may be significantly less than the return on a direct investment in the securities comprising the underlying indices during the term of the securities. The securities may be called prior to the maturity date. If the securities are called early, the holding period over which you will receive contingent quarterly payments could be as little as 3 months.

If the securities are redeemed prior to the maturity date, you will receive no more contingent quarterly payments. There is no guarantee that you would be able to reinvest the proceeds from an investment in the securities at a comparable return for a similar level of risk following an automatic call. You are exposed to the market risk of all underlying indices, with respect to both the contingent quarterly payments, if any, and the payment at maturity, if any.

Your return on the securities is not linked to a basket consisting of the 2 underlying indices. Rather, it will be contingent upon the independent performance of each underlying.

Unlike an instrument with a return linked to a basket of underlying assets, in which risk is potentially mitigated and diversified among all the components of the basket, you will be exposed to the risks related to both of the underlying indices. Poor performance by any underlying index over the term of the securities may negatively affect your return and will not be offset or mitigated by any positive performance by the other underlying index.

To receive any contingent quarterly payments, all underlying indices must close at or above their respective coupon barrier levels on the applicable determination date. In addition, if any underlying index has decreased to below its respective downside threshold level as of the final determination date, you will be fully exposed to the decrease in the worst performing underlying index on a 1 to 1 basis, even if the other underlying index has appreciated.

Accordingly, your investment is subject to the market risk of each of the underlying indices. Because the securities are linked to the performance of the worst performing underlying index, you are exposed to greater risks of receiving no contingent quarterly payments and sustaining a significant loss on your investment than if the securities were linked to just one underlying index.

The risk that you will not receive any contingent quarterly payments, or that you will suffer a significant loss on your investment, is greater if you invest in the securities as opposed to substantially similar securities that are linked to the performance of just one underlying index. With 2 underlying indices, it is more likely that one or both of the underlying indices will close below their respective coupon barrier levels on any determination date including the final determination date and below its downside threshold level on the final determination date, than if the securities were linked to only one underlying index.

Therefore, it is more likely that you will not receive any contingent quarterly payments, and that you will suffer a significant loss on your investment. In addition, because each underlying index must close above its initial index level on a quarterly determination date in order for the securities to be called prior to maturity, the securities are less likely to be called than if the securities were linked to just one underlying index.

The amounts payable on the securities are not linked to the levels of the underlying indices at any time other than on the determination dates, including the final determination date. The payments on the securities will be based on the closing levels of the underlying indices on each determination date, subject to postponement for non-trading days and certain market disruption events.

Even if the level of an underlying index appreciates prior to an applicable determination date but then drops on that day to a level that is below its coupon barrier level, the contingent quarterly payment on the securities will not be payable for that determination date. Similarly, even if the level of an underlying index appreciates prior to the final determination date but then decreases on that day to a level that is below its downside threshold level, the payment at maturity will be less, and may be significantly less, than it would have been had the securities been linked to the levels of the underlying indices on a date prior to the final determination date.

Although the actual levels of the underlying indices on the maturity date or at other times during the term of the securities may be higher than their levels on one or more determination dates, the payments on the securities will be based solely on the levels of the underlying indices on the determination dates.

The market price of the securities will be influenced by many unpredictable factors. The level of each underlying index may be, and has recently been, volatile, and we can give you no assurance that the volatility will lessen. You may receive less, and possibly significantly less, than the stated principal amount if you try to sell your securities prior to maturity. The securities are senior unsecured debt obligations of the Issuer, HSBC, and are not, either directly or indirectly, an obligation of any third party.

As further described in the accompanying prospectus supplement and prospectus, the securities will rank on par with all of the other unsecured and unsubordinated debt obligations of HSBC, except such obligations as may be preferred by operation of law. Any payment to be made on the securities depends on the ability of HSBC to satisfy its obligations as they come due. As a result, the actual and perceived creditworthiness of HSBC may affect the market value of the securities and, in the event HSBC were to default on its obligations, you may not receive the amounts owed to you under the terms of the securities and could lose your entire investment.

Investing in the securities is not equivalent to investing in the securities comprising the underlying indices. Investing in the securities is not equivalent to investing in the component securities of any underlying index. Investors in the securities will not have voting rights or rights to receive dividends or other distributions or any other rights with respect to the securities comprising the underlying indices.

The RTY tracks companies that may be considered small-capitalization companies. These companies often have greater stock price volatility, lower trading volume and less liquidity than large-capitalization companies and therefore the respective index level may be more volatile than an investment in stocks issued by larger companies.

Stock prices of small-capitalization companies may also be more vulnerable than those of larger companies to adverse business and economic developments, and the stocks of small-capitalization companies may be thinly traded, making it difficult for the RTY to track them. The interrupt enable bit ICR. This avoids pipeline side effects and eliminates the need for an ISYNC synchronize instruction stream following these instructions.

The values in these respective bits are used as follows: IE to restore the state of this bit. The interrupted routine then continues. The Interrupt Vector Table is stored in code memory. This address is loaded in the program counter. Interrupt vectors are ordered in the table by increasing priority.

With this arrangement, it is possible to have multiple Interrupt Vector Tables and switch between them by changing the contents of the BIV register.

Execution of the ISR begins at this address. Due to this operation, it is recommended that bits [ Note that bit 0 of the BIV register is always 0 and cannot be written to instructions have to be aligned on even byte boundaries. If an interrupt handler is very short it may fit entirely within the 8 words available in the vector code segment. Otherwise the code stored at the entry location can either span several vector entries, or should contain some initial instructions followed by a jump to the rest of the handler.

The default on power-up is fixed to H, however the BIV register can be written to using the MTCR instruction during the initialization phase of the system, before interrupts are enabled. It is also possible to have multiple interrupt vector tables and switch between them simply by modifying the contents of the BIV register.

Spanning eliminates the need of a jump to the rest of the interrupt handler if it would not fit into the available eight words between entry locations. Note that priority numbers relating to entries occupied by a spanned service routine must not be used for any of the active Service Request Nodes SRNs which request service from the same service provider. In Figure Page , vector locations three and four are covered through the service routine for entry two.

Therefore these numbers must not be assigned to SRNs requesting CPU service, although they can be used to request another service provider. The next available vector entry is now entry five. Use of this technique increases the range of priority numbers required in a given system, but the size of the vector table must be adjusted accordingly. These groups are easily created with the TriCore interrupt system architecture.

This blocks all further interrupts from being serviced until the interrupt system is either enabled again through software, or the service routine is terminated with the RFE Return From Exception instruction. This will be one ICE. This includes a re-occurrence of the current interrupt; i. A potential problem that is easily overcome in the TriCore architecture is that application requirements often require interrupt requests of similar significance to be grouped together in such a way that no request in that group can interrupt the ISR of another member of the same group.

Creating these Interrupt Priority Groups is easily accomplished in the interrupt system. For a defined group of interrupt requests, the software of their respective service routines sets the CCPN to the number of the highest SRPN used in that group, before enabling the interrupt system again. Figure shows an example. Every time one of the interrupts from group one is serviced, the service routine sets the CCPN to 12, the highest number in that group, before re-enabling the interrupt system.

Every time one of the interrupts from group two is serviced, the service routine sets the CCPN to 17 before reenabling the interrupt system. If interrupt 14 is serviced for example, it can only be interrupted by requests with a priority number higher than 17, but not through a request from its own priority group or requests with lower priority.

One can see the flexibility of this system and its superiority over systems with fixed priority levels. Setting the CCPN to the maximum number in each service routine has the same effect as not enabling the interrupt system again; i. The flexibility for interrupt priority levels ranges from all interrupts being in one group, to each interrupt request building its own group, and all possible combinations in between.

For example, an interrupt is placed on a very high priority because response time and reaction to an event is critical, but further operations in that service routine can run on a lower priority.

In this instance the service routine would be divided into two parts, one containing the critical actions, the other part the less critical ones. The priority of the interrupt node is first set to the high priority, so that when the interrupt occurs the necessary actions are carried out immediately. The priority level of this interrupt is then lowered and the interrupt request bit is set again via software indicating a pending interrupt while still in the service routine.

Returning to the interrupted program terminates the high priority service routine. The pending interrupt is serviced when the CPU priority is lower than its own priority. After entering the service routine, which is now at a different address in the program memory, the outstanding but low-priority actions of the interrupt are performed.

To prevent any interruption the TriCore architecture allows the priority level of the service request to be raised within the ISR, and also allows interrupts to be completely disabled.

This can be achieved simply by assigning different Service Request Priority Numbers SRPNs at different times to an interrupt source depending on the application needs.

Usually the ISR for that interrupt executes different code depending on its priority. In traditional interrupt systems, the ISR would have to check the current priority of that interrupt request and perform a branch to the appropriate code section, causing a delay in the response to the request. In the TriCore system however, the interrupt will automatically have different vector entries for the different priorities. An extra check and branch in the ISR is not necessary, therefore the interrupt latency is reduced.

The use of different priority numbers for one interrupt has to be taken into consideration when creating the vector table.

Once the interrupt request bit in a service request control register is set, there is no way to distinguish between a software-posted interrupt request and a hardware interrupt request. For that reason it is generally advisable to use Service Request Nodes and interrupt priority numbers for software-posted interrupts that are not used for hardware interrupts, such as interrupts which are triggered by a peripheral module.

However the number of hardware SRNs available in a given system for such purposes depends on the application requirements. To support the use of software-posted interrupts, principally for RTOS code, the architecture provides a number of Service Request Nodes which are intended solely for the purpose of software-posting. They are not connected to any peripheral or any other module on the chip, and the service request flag can only be set by software.

ISRs whose actions affect the launching of software-managed tasks post a software interrupt request at priority level one to signal the change. There is no need for an exit function to check whether the ISR is returning to the background task level or to a lower priority ISR that it interrupted, in order to determine when to invoke the task dispatch function.

When there is a pending interrupt at a priority higher than the return context for the current interrupt, this interrupt will then be serviced. When a return to the background task level is performed the software-posted interrupt at priority level one will automatically be recognized and serviced. The BIV register holds the base addresses for the interrupt vector tables. Special instructions control the enabling and disabling of the interrupt system. See the relevant documentation for a specific TriCore product implementation.

It indicates the priority number of the pending service request. PIPN is set to 0 when no request is pending, and at the beginning of each new arbitration process. No valid pending request. Request pending, lowest priority. Request pending, highest priority.

IE is cleared to 0 when an interrupt is taken, and is restored to the previous value when the ISR executes an RFE instruction to terminate itself. Interrupt system is globally disabled. Interrupt system is globally enabled. When an interrupt is accepted, the entry address into the interrupt vector table is generated from the priority number taken from the PIPN of that interrupt, left shifted by five bits, and then ORd with the contents of the BIV register.

The left-shift of the interrupt priority number results in a spacing of 8 words 32 bytes between the individual entries in the vector table. Because of the simple ORing of the left-shifted priority number and the contents of the BIV register, the alignment of the base address of the vector table must be to a power of two boundary, dependent on the number of interrupt entries used.

For the full range of interrupt entries an alignment to an 8 KByte boundary is required. If fewer sources are used, the alignment requirements are correspondingly relaxed. Traps are always active; they cannot be disabled by software action.

Each class has its own trap handler, accessed through a trap vector of 32 bytes per entry, indexed by the hardware-defined trap class number. Within each class, specific traps are distinguished by a Trap Identification Number TIN that is loaded by hardware into register D[15] before the first instruction of the trap handler is executed.

The trap handler must test and branch on the value in D[15] to reach the subhandler for a specific TIN. Traps can be further classified as synchronous or asynchronous, and as hardware or software generated. These are explained after the following table which lists the trap classes, summarising and classifying the pre-defined set of specific traps within each class.

In the following table: HW Virtual Address Fill. HW Virtual Address Protection. Page 2 MPR Synch. HW Memory Protection Read. Page 3 MPW Synch. HW Memory Protection Write. Page 4 MPX Synch. HW Memory Protection Execution. Page 5 MPP Synch.

Page 6 MPN Synch. Page 3 OPD Synch. HW Invalid Operand specification. Page 4 ALN Synch. HW Data Address Alignment. Page 5 MEM Synch. Page 2 CDO Synch. HW Call Depth Overflow. Page 3 CDU Synch. HW Call Depth Underflow. Page 4 FCU Synch.

Page User Manual Volume 1 V1. RFE with non-zero call depth. Page 2 DSE Synch. Page 3 DAE Asynch. SW Sticky Arithmetic Overflow. Page SW System Call. Page Non-Maskable Interrupt. The range of values that can be specified is 0 to , inclusive. The instruction causing the trap is known precisely. The trap is taken immediately and serviced before execution can proceed beyond that instruction.

Some result indirectly from instructions that have been previously executed, but the direct association with those instructions has been lost. The difference between an asynchronous trap and an interrupt is that asynchronous traps are routed via the trap vector instead of the interrupt vector. They can not be masked and they do not change the current CPU interrupt priority number. In most, but not all cases, the exception conditions are associated with the attempted execution of a particular instruction.

Examples User Manual Volume 1 V1. CCPN field is not updated. The vectors are made up of a number of short code segments, evenly spaced by eight words. If a trap handler is very short it may fit entirely within the eight words available in the vector code segment. If it does not fit the vector code segment then it should contain some initial instructions, followed by a jump to the rest of the handler.

The trap identifier has two components: For a synchronous trap, the return address is the PC of the instruction that caused the trap. For an asynchronous trap, the return address is that of the instruction that would have been executed next, if the asynchronous trap had not been taken. The return address for an interrupt follows the same rule. It can be assigned to any available code memory. This arrangement makes it possible to have multiple Trap Vector Tables and switch between them by changing the contents of the BTV register.

When a trap event occurs, a trap identifier is generated by the hardware detecting the event. Because of this operation, it is recommended that bits [7: Note that bit 0 of the BTV register is always 0 and can not be written to instructions have to be aligned on even byte boundaries. If a trap handler TSR is very short, it may fit entirely within the eight words available in the Trap Vector Table entry. Otherwise, the code at the entry point must ultimately cause a jump to the rest of the TSR residing elsewhere in memory.

The return address in A[11] is updated. The TIN is loaded into D[15]. The stack pointer bit is set for using the interrupt stack: The current Protection Register Set is set to 0: The trap vector table is accessed to fetch the first instruction of the trap handler. Although traps leave the ICR. CCPN unchanged, their handlers still begin execution with interrupts disabled.

They can therefore perform critical initial operations without interruptions, until they specifically re-enable interrupts. For the non-recoverable FCU trap, the initial state is different. The upper context cannot be saved. Only the following states are guaranteed: The trap vector table is accessed to fetch the first instruction of the FCU trap handler.

The following internal Protection Traps are defined: A table of instructions which are restricted to Supervisor mode or User-1 mode, is supplied in the Instruction Set chapter of Volume 2 of this manual. T instruction does not lie within any range with read permissions enabled. T instruction does not lie within any range with write permissions enabled. Instruction errors include errors in the instruction opcode, in the instruction operand encodings, or for memory accesses, in the operand address.

An invalid opcode is one that does not correspond to any instruction known to the implementation. An unimplemented opcode corresponds to a known instruction that is not implemented in a given hardware implementation. The instruction may be implemented via software emulation in the trap handler. Example UOPC conditions are: An external coprocessor instruction if the external coprocessor is not present. The OPD trap may also be raised for other cases where operands are invalid. Implementations are not architecturally required to raise this trap, and may treat invalid operands in an implementation defined manner.

An ALN trap is also raised when the size, length or index of a circular buffer is incorrect. It must also document any other implementation specific MEM traps it will raise.

Architectural constraints which will raise the MEM trap are: The operation responsible for the context save completes normally and then the FCD trap is taken. If the operation responsible for the context save was the hardware interrupt or trap entry sequence, then the FCD trap handler will be entered before the first instruction of the original interrupt or trap handler is executed. The return address for the FCD trap will point to the first instruction of the interrupt or trap handler.

The FCD trap handler is normally expected to take some form of action to rectify the context list depletion. The nature of that action is OS dependent, but the general choices are to allocate additional memory for CSA storage, or to terminate one or more tasks, and return the CSAs on their call chains to the free list.

A third possibility is not to terminate any tasks outright, but to copy the call chains for one or more inactive tasks to uncached external or secondary memory that would not be directly usable for CSA storage, and release the copied CSAs to the free list.

In that instance the OS task scheduler would need to recognize that the inactive task's call chain was not resident in CSA storage, and restore it before dispatching the task. In addition, it is possible that an asynchronous trap condition, such as an external bus error, will be reported after the FCD trap has been taken, interrupting the FCD trap handler and using one more CSA.

Therefore, to avoid the possibility of a context list underflow, the free context list must include a minimum of two CSAs beyond the one pointed to by the LCX register.

If the bit is found to be set, the asynchronous trap handler must avoid making any calls, but should queue itself in some manner that allows the OS to recognize that the trap occurred.

It should then carry out an immediate return, back to the interrupted FCD trap handler. COUNT at its maximum value. A call depth underflow does not necessarily reflect a software error in the currently executing task. An OS can achieve finer granularity in call depth counting by using a deliberately narrow Call Depth Counter, and incrementing or decrementing a separate software counter for the current task on each call depth overflow or underflow trap.

A program error would be indicated only if the software counter were already zero when the CDU trap occurred. The FCU trap is also taken if any error is encountered during a context save or restore operation.

The context operation cannot be completed. In failing to complete the context save or restore, architectural state is lost, so the occurrence of an FCU trap is a non-recoverable system error. The FCU trap handler should ultimately initiate a system reset.

This trap indicates a system software error kernel or OS in task setup or context switching among software managed tasks SMTs. No software error or combination of errors in a user task can generate this condition, unless the task has been allowed write permission to the context save areas which, in itself, can be regarded as a system software error. UL bit, is incorrect for the type of restore attempted; i. As with the CSU trap, this indicates a system software error in context list management.

The return from an interrupt or trap handler should normally occur within the body of the interrupt or trap handler itself, or in code to which the handler has branched, rather than code called from the handler. If this is not the case there will be one or more saved contexts on the residual call chain that must be popped and returned to the free list, before the RFE can be legitimately issued.

In the case of an error during the data load phase of a data cache refill. There are implementation-dependent registers for DSE which can be interrogated to determine the source of the error more precisely. Refer to the User's Manual for a specific TriCore implementation for more details. Generally this means an error returned on the system bus from a peripheral or external memory. This DAE trap is raised when: There is an error caused by a cache management instruction.

There is an error caused by a cache line writeback. There are implementation-dependent registers for DAE which can be interrogated to determine the source of the error more precisely. Examples of typical errors that can cause a CAE trap are unimplemented coprocessor instructions and arithmetic errors as found in the Floating Point Unit for example.

CAE is shared amongst all coprocessors in a given system. A trap handler must therefore inspect all coprocessors to determine the cause of a trap. The trap is synchronous to the erroneous instruction. A PIE trap is raised if any element within the fetch group contains an unrecoverable error. Hardware is not required to localise the error to a particular instruction. An implementation may provide additional registers that can be interrogated to determine the source of the error more precisely.

Refer to the User manual for a specific Tricore implementation for more details. Implementations may choose to implement the DIE trap as either an asynchronous or synchronous trap. A DIE trap is raised if any element accessed by a load or store contains an uncorrectable error. Hardware is not required to localise the error to the access width of the operation. This may be used to guard against task overrun in time critical applications.

Typically there is an external pin that can be used to signal the NMI, but it may also be raised in response to such things as a watchdog timer interrupt, or an impending power failure. Asynchronous trap highest priority. The following trap rules must also be considered: The older the instruction in the instruction sequence which caused the trap, the higher the priority of the trap. All potential traps from younger instructions are void.

This trap takes priority over all other exceptions. When the same instruction causes several synchronous traps anywhere in the pipeline, priorities from highest 1 to lowest follow those shown in the following table. When a trap occurs, the entry address into the trap vector table is generated from the Trap Class of that trap, left-shifted by 5 bits and then ORd with the contents of the BTV register. The left-shift of the Trap Class results in a spacing of 8 words 32 bytes between the individual entries in the vector table.

Also, due to the simple ORing of the left-shifted trap identification number and the contents of the BTV register, the alignment of the base address of the vector table must be to a power of two boundary. There are eight different trap classes, resulting in Trap Classes from 0 to 7. The contents of the register are implementation specific. Uncorrectable Memory Integrity Error If hardware is not able to provide the expected data to the core on accessing a memory element containing a memory integrity error, the memory integrity error is defined as being uncorrectable.

Correctable Memory Integrity Error If hardware is able to provide the expected data to the core on accessing a memory element containing a memory integrity error, the memory integrity error is defined as being correctable. Correctable memory integrity errors are further categorized as either Resolved or Unresolved. Correctable memory integrity errors always provide the correct data to the core.

As part of the correction process hardware may also update the erroneous source data in memory with the corrected data. Such a memory integrity error is defined as being Resolved.

If the erroneous source data in memory is not updated the memory integrity error is defined as being Unresolved. The trap is of Class 4 and TIN 5. Implementation specific registers that can be interrogated to more precisely determine the source of the error. Refer to the User manual for a specific Tricore product for details.

The trap is of Class 4 and TIN 6. A TriCore implementation may choose to implement the DIE trap as either an asynchronous or synchronous trap. Implementation specific registers can be interrogated to more precisely determine the source of the error.

Refer to the User manual for a specific Tricore product for more details. Each register contains two count fields, one for resolved corrected errors and one for unresolved corrected errors. The counter saturates at the value FFH. The CCPIE-U counter is incremented on each detection of a corrected-unresolved memory integrity error in the local instruction memories.

In local instruction memory. In local data memory. The contents of these registers are implementation specific. The register is architecturally defined, however the register contents are implementation specific. These attributes are defined by groups of physical memory properties.

For example, an address that does not have the cacheable property C, would be described as Non-cacheable C. The following definitions refer to the concept of necessary and speculative accesses: Speculative accesses are those that an implementation may make in order to improve performance either in correct or incorrect anticipation of a necessary access. No User-0 mode data access is possible. All accesses are exempt from the protection system settings.

PTE translation where the physical address targets a region with this property results in undefined behaviour. A speculative data access is a read access to memory addresses that are not strictly necessary for correct program execution. The processor never performs speculative write accesses which are visible in a memory region. The fetch property allows full speculation on all fetch accesses to the region.

The cacheable property has no affect on the amount or range of speculation of code fetches. If a necessary fetch access is directed by program flow to a physical memory region that does not have the fetch property then a PSE Program fetch Synchronous Error trap occurs.

If a data access is directed by necessary program flow to a physical memory region that does not have the Data Access property, then a DSE Data access Synchronous Error trap occurs.

For data accesses, the interpretation of the combinations of the Privileged Peripheral, Cacheable and Speculative properties for a memory region are defined in Table All other combinations of these three properties not present in this table, are reserved. Non-Cached access P C S The processor may read an entire cache line1 containing the address of a necessary access and place it in a buffer for subsequent accesses.

The order of accesses is not guaranteed 2. Full Speculation P C S The processor may perform speculative read accesses to entire cache lines in physical memory and place them in the cache. The order of accesses is not guaranteed. Examples of implemented cache lines are bytes and bytes, but may be smaller or larger.

The architecture defines three attributes: Each segment has its own physical memory attribute. The default defined attributes are shown in the following table: There are two different scratchpad RAMs: The size of the scratchpad RAMs is implementation dependent. The cacheable property is only relevant for accesses in the ranges: There are three sources of permission for a memory access: A memory access is not valid if the address of the access is to an unimplemented region of memory or is misaligned; therefore an access can be permitted but not valid.

The PS and MMU act upon the direct translation and virtual translation paths respectively, therefore the permission for a memory access that undergoes virtual translation lies only with the MMU, not the PS, and vice-versa. Note that when changing the value of the PMA0 register, an implementation may require additional operations to be performed in order to maintain coherency of the processors view of memory. Segment-F is constrained to be peripheral space in all implementations. The physical memory attributes of all other segments are implementation defined.

Segment FH is constrained to always be peripheral space see Table The contents of these registers where implemented is implementation dependent.

Implementation Specific 22 21 20 19 18 17 16 5 4 3 2 1 0 Implementation Specific 15 14 13 12 11 10 9 8 7 6 Implementation Specific - Field Bits Type Implementation [ The system is unobtrusive, imposing little overhead and avoids non-deterministic run-time behaviour. The protection system incorporates hardware mechanisms that protect user-specified memory ranges from unauthorized read, write, or instruction fetch accesses.

The protection hardware can also facilitate application debugging. The TriCore architecture contains eight trap classes and these are further classified as synchronous or asynchronous, hardware or software. This allows systems to be implemented efficiently, without the loss of security inherent in running in Supervisor mode. Memory Protection Provides control over which regions of memory a task is allowed to access, and what types of access is permitted.

Range Based The range-based memory protection system is designed for small and low cost applications to provide coarsegrained memory protection for systems that do not require virtual memory. This range-based system is detailed in this chapter. Effective Addresses Effective addresses are translated into physical addresses using one of two translation mechanisms: Memory protection for addresses that undergo direct address translation is enforced using the range-based memory protection system described in this chapter.

An address belongs to the range if: The granularity for lower and upper boundaries is 8-bytes. Access Permissions Access Permissions define the kind of access allowed to a protection range. The available types are: Each Protection Set consists of: The number of memory protection sets provided is specific to each TriCore implementation, limited to a minimum of two and a maximum of four.

Having multiple protection sets allows for a rapid change of the whole set of access permissions when switching between User and Supervisor mode, or between different User tasks. At any given time one of the sets is the current protection register set which determines the legality of memory accesses by the current task. PRS field determines the current protection register set number. For example, an implementation with 16 data protection ranges and 8 code protection ranges has 8 data range pairs and 4 code range pairs.

For each protection set one protection range out of each pair is selected. The selection of the protection ranges is controlled by Range Select RS flags in the data and code protection set configuration registers. For each Range Pair a corresponding Range Select flag chooses either the first or the second range of the pair.

A protection set has up to 8 RS flags for selecting Code Ranges and up to 8 RS flags for selecting Data Ranges, depending on the number of protection ranges implemented. If one of the ranges allows it, the memory access is permitted.

This means that when two ranges intersect, the intersecting regions will have the permission of the most permissive range. In this situation it is implementation defined not architecturally defined as to whether or not a memory protection trap is taken. To ensure deterministic behaviour in all implementations of TriCore, a region at least twice the size of the largest memory accesses, minus one byte, should be left as a buffer between each memory protection region.

Some implementations may require less spacing between buffers, please refer to implementation specific documentation for details. The legality is determined by all of the following: PRS The ranges selected in the protection register set The access permissions set for the ranges selected for the protection set 9.

Instruction fetch addresses are checked against the currently selected code address range tables. The mode entries for the data range table entries enable only read and write accesses, while the mode entries for the code range table entries enable only execute access.

In order for data to be read from program space, there must be an entry in the data address range table that covers the address being read. Conversely there must be an entry in the code address range table that covers the instruction being read. The protection system does not differentiate between access permission levels.

The data and code protection settings have the same effect, whether the permission level is currently set to Supervisor, User-1 or User-0 mode. For instruction fetches, the PC value for the fetch is checked against the selected code protection ranges for the current protection set. When a PC is found to fall outside of all of the selected ranges, then permission for the access is denied. When an address is found to fall within one of the selected ranges the associated access permission is checked and the access allowed or denied as appropriate.

For load and store operations, data address values are checked against the selected data protection ranges for the current protection set. When an address is found to fall outside of all of the selected ranges then permission for the access is denied. When an address is found to fall within an enabled range the access is permitted. When an address is found to fall within one of the selected ranges the associated access permissions are checked and access is allowed or denied as appropriate.

Supervisor mode does not automatically disable memory protection. The Protection register set that is selected for Supervisor mode tasks Set-0 will normally be set up to allow write access to regions of memory that are protected from User mode access. In addition Supervisor mode tasks can execute instructions to change the protection maps, or to disable the protection system entirely.

As Supervisor mode does not implicitly override memory protection it is possible for a Supervisor mode task to take a memory protection trap. The protection system does not apply to accesses in memory regions with the peripheral space or emulator space attribute. If a memory access is attempted to either of these segments, the access is permitted by the protection User Manual Volume 1 V1. Saves or restores of contexts to the context save area do not require the permission of the protection system to proceed.

The examples concentrate on data-side protection, but apply equally to code-side protection. Separate Protection Register Sets may be used for different tasks, to allow for quick task switching without the need to reload all the protection registers. Typically in Supervisor Mode Kernel Mode , unrestricted access is allowed to the whole address space, while accurately defining access for Tasks may require the use of multiple protection ranges. A sample range allocation is illustrated in Figure The register settings for this example are shown in the following table: In this way the protection resources can be used more effectively and flexibly, allowing for more precise definition of access permission.

Figure illustrates a sample memory space: The register settings for this example are given in Table Implementation Specific Reset Value: Data write accesses to associated address range not permitted.

Data write accesses to associated address range permitted. Address Field Read Enable 0: Data read accesses to associated address range not permitted. Data read accesses to associated address range permitted. Instruction fetch accesses to associated address range not permitted. Instruction fetch accesses to associated address range permitted.

In backward compatibility mode: The system consists of two independent decrementing 32 bit counters, arranged to generate a Temporal Asynchronous Exception TAE trap Class-4, Tin-7 , on decrement to zero. After activation, the timer will decrement by one on each CPU clock cycle. This ensures that no time-out event is missed during the handling of another TAE trap. Writing a non-zero value starts the Timer.

Read returns the current Timer value. Any subsequent TAE traps are disabled. A write clears the flag and re-enables TAE traps. It need not be present in every system that uses the core, and even when present it can be disabled. Conversion to or from IEEE single precision format from or to TriCore signed and unsigned integers and bit signed fractions Q31 format.

F instruction used to obtain an approximate value intended for use in Newton-Raphson iterations to perform a square-root operation. Comparison of two floating-point numbers. All four IEEE rounding modes are implemented. Restrictions The FPU has the following restrictions and usage limitations: IEEE denormalized numbers are not supported for arithmetic operations. IEEE compliant remainder function cannot be implemented using FPU instructions because of the effects of multiple rounding when using a sequence of individually rounded instructions.

Full compliance with the IEEE standard is not achieved because denormal numbers are not supported. For normal numbers the mantissa has an implied 1 immediately to the left of the binary point. Table shows the different types of number representation in IEEE single precision format. Both signed values of zero are always treated identically and never produce different results except different signed zeros.

With the exception of the CMP. F instruction, all instructions replace denormal operands with the appropriately signed zero before computation. Following computation, if a denormal number would otherwise be the result, it is replaced with the appropriately signed zero. Conceptually, the conventional order for making IEEE computations is: Compute result to infinite precision.

Round to IEEE format. This is replaced with: Substitute signed zero for all denormal operands. Substitute signed zero for all denormal results. This procedure has a subtle effect on underflow; see Round to Nearest: Denormals and Zero Substitution, page Denormal numbers are supported only by the CMP. F instruction which makes comparisons of denormal numbers in addition to identifying denormal operands.

There are two types of NaNs: When invalid operations are performed including operations with a signalling NaN operand , FI is asserted and a quiet NaN is produced as the floating-point result.

IEEE requires two conditions to occur before flagging underflow: IEEE allows this to be detected either before or after rounding. There must be a loss of accuracy in the stored result. Loss of accuracy can be detected in two ways: Denormalization loss occurs when the result is calculated assuming an unbounded exponent, but is rounded to a normalized number using 23 fractional bits.

If this rounded result must be denormalized to fit into IEEE format and the resultant denormalized number differs from the normalized result with unbounded exponent range, then a denormalization loss occurs. An inexact result is one where the infinitely precise result differs from the value stored.

The FPU determines tininess before rounding and inexact results to determine loss of accuracy. In the case of the FPU, even if a denormal result would produce no loss of accuracy, because it is replaced with a zero, accuracy is lost and underflow must be flagged. Any tiny number that is detected must therefore result in a loss of accuracy since it will either be a denormal that is replaced with zero or rounded up. Therefore underflow detection can be simplified to tiny number detection alone; i.

F can give different results from using separate multiply MUL. F and accumulate ADD. F operations because the result is only rounded once at the end of a MAC. Under these circumstances the results returned by arithmetic operations may differ from IEEE requirements to allow intermediate results to be passed to the trap handling routines. These traps are provided to assist in debugging routines and operations. Remainder FPU instructions cannot be used to implement the remainder function because of the errors that can occur from multiple rounding.

For reference, the IEEE method for calculating remainder is given below. Note that rounding must only occur on the conversion to integer, and for the final result. Convert between binary and decimal - 1 Round to nearest. The infinitely precise result is the mathematically exact result that would be computed by the operation, if the number of mantissa and exponent bits were unlimited.

This is the default rounding mode that should be selected when RTOS software initializes a task. See Round to Nearest: Even, page , for further information. Round toward zero is defined as returning the representable value that is closest to and no greater in magnitude than the infinitely precise result. It is equivalent to truncation. Rounding is performed at the end of each relevant FPU instruction, followed by the replacement of all denormal numbers with the appropriately signed 0.

F that combine multiplication and addition in a single operation. Instead the whole MAC is calculated with infinite precision and rounded at the end of the add. It is therefore possible that the result from a MADD. F instruction will differ from the result that would be obtained using the same operands in a MUL.

F followed by an ADD. Rounding Mode Restored TriCore 1. If two representable values are equally close i. This is sometimes known as rounding to nearest even. This is usually straight forward, but if the infinitely precise result is half way between two representable numbers with different exponents, the result with the larger exponent is always selected the LSB of its mantissa is zero.

For example, if the infinitely precise result is: Denormals and Zero Substitution Following computation, results are first rounded to IEEE representable numbers and then the appropriately signed zero is substituted for any denormal results that may have occurred. This produces some results that can seem counter intuitive. Consider an infinitely precise result that has been computed and falls between the smallest representable positive IEEE normal number 1.

If the infinitely precise result is nearer to the denormal number, then the result is rounded to the denormal value. Zero is then substituted for the denormal result. The FPU architecture cannot produce denormal results, however the concept of denormal numbers is important to the FPU. Denormals and Zero Substitution Following computation results are first rounded to IEEE representable numbers, then the appropriately signed zero is substituted for any denormal results that may have occurred.

See Denormal Numbers, page However if a positive negative result would otherwise be rounded to a denormal number, it is then substituted for a zero.

Therefore the returned result of zero is less than greater than the infinitely precise result. The returned result appears to contradict the definition of these rounding modes in this case. When one of these exceptions occur the corresponding exception flag in the PSW is asserted.

Asynchronous Traps TriCore 1. In accordance with IEEE, each bit is sticky so that the FPU instructions in general assert these flags when an exception occurs and do not negate them when the exception does not occur.

Note that the PSW bits used to store the exception flags are also used to store ALU flags as shown in the table above.

Conversions from floating-point to other formats where the rounded result is outside the range of the target. When an instruction that produces a floating-point result asserts FI as a result of a signalling NaN or invalid operation, the result is a quiet NaN.

F with a negative operand. F with 0 as both operands. FI is only asserted when one of these NaNs is signalling. See NaNs Not a Number , page Refer to the instruction description for what the result should be. The result returned is determined by the rounding mode and the sign of the unrounded result: When overflow is flagged FV asserted , the returned result can not be exactly equal to the unrounded result.

Therefore whenever FV is asserted FX is also asserted. F if the divisor operand is zero and the dividend operand is a finite non zero number. The result is an infinity with sign determined by the usual rules. The return result for instructions flagging an underflow are complicated by the way that FPU treats denormal numbers. This is described in detail in Round to Nearest: FX - Inexact If the rounded result of an operation is not exactly equal to the unrounded result, then the FX flag is set.

The result delivered is the rounded result, unless either overflow FV or underflow FU has also occurred during this instruction, when the overflow or denormalization return result rules are followed. FPU CAE traps should not be confused with the synchronous exception traps optional to IEEE which allow software routines to correct arithmetic overflow or underflow.

The FPU CAE trap is intended for debug purposes only and has no effect on either the exceptional instruction or any other instruction which may be executing within the FPU.

The result returned by an exceptional instruction causing a CAE trap is identical to that which would be returned if no trap were taken.

The CAE trap is signalled after instruction completion. Any number of these enable bits may be set to allow traps to be taken if any of a range of exceptions occur. FX is a regularly occurring condition, care should be taken in enabling this trap. When an instruction causes one of the enabled exceptions, information about the exceptional instruction including the instruction PC, opcode and source operands are captured in the FPU special function registers.

This avoids multiple traps being generated from the same root problem and the original information being lost. TST bit may be cleared to enable further traps.

The result of the exceptional instruction causing a trap is not stored in an FPU register. Only valid when TST is asserted. Note that this is the rounding mode supplied to the FPU for the exceptional instruction.

UPDFL instructions may cause a trap and change the rounding mode. In this case the RM bits capture the input rounding mode. Clears the trapped instruction TST will be negated. TST 0 rh Trap Status 0: The next enabled exception will cause the exceptional instruction to be captured. No further enabled exceptions will be captured until TST is cleared.

Data general purpose register 0. Data general purpose register Users are advised that mechanisms may differ in subsequent architecture generations.

It offers real-time run control and internal visibility of resources such as data and memories. Access and update internal registers and core local memory. Setting breakpoints and watchpoints with complex trigger conditions. DE bit is controlled and how the CDC is enabled or disabled, is system dependent.

When the CDC is enabled, the core is said to be in debug mode. This signal can be controlled by writes to the Debug Status register, whereas the Core Break-Out signal can not. Debug Events that can cause a Debug Action: Debug Actions can be one or more of the following: The reading and writing of other system memory while the CPU is running can be intrusive, depending on the number of cycles that are required to perform the operation. When this happens, cycle stealing occurs.

The detection of Debug Events has no effect on real-time execution. A hardware Event generation unit. It may take several clocks for the Debug Event to be recognized by the CPU if it is currently executing a multi-cycle, non-cancellable instruction such as a context save and restore for example. This feature facilitates software debug, which allows a jump to a monitor program and provides a relatively inexpensive software instrumentation and interrogation mechanism.

This gives the debug software the ability to monitor, detect and modify changes to CSFRs. Configuring the Debug Controller or accessing Performance counters will not cause a debug event. Debug Triggers are either: Compared addresses are virtual addresses. These Debug Triggers provide the inputs to a programmable block of logic which produces Debug Events as its output see Debug Triggers pg 5.

Pairs of debug trigger addresses are used to define address ranges. Execution of an instruction within a range of addresses. Loading a value from a specific address. Loading a value from within a range of addresses.

Storing a value to a specific address. Storing a value to within a range of addresses. The number of available debug triggers is implementation dependent. A trigger will be generated for an address in the range. This register contains the accumulated state of the debug triggers since the register was last cleared. For range comparisons only the lower trigger activation is recorded. Note that it is implementation dependent whether or not this signal is connected to an external pin.

Halt mode performs a cancel of: All instructions after the instruction that caused the breakpoint if BBM is clear. Once these instructions have been cancelled the CPU enters Halt mode, where no more instructions are fetched or executed. HALT bit field is set to 01B.

Once in Halt mode the external Debug system is used to interrogate the target through the mapping of the architectural state into the FPI address space. It relies upon the following emulator resources: This is used to store the critical state during the Debug Monitor entry sequence.

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Instruction fetch accesses to associated address range not permitted. A hardware Event generation unit.

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Figure shows the steps taken during the context restore operation.

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